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Espressif Systems /ESP32-P4 /ADC /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (START_FORCE)START_FORCE 0 (START)START 0WORK_MODE 0 (SAR_SEL)SAR_SEL 0 (SAR_CLK_GATED)SAR_CLK_GATED 0SAR_CLK_DIV0SAR1_PATT_LEN 0SAR2_PATT_LEN 0 (SAR1_PATT_P_CLEAR)SAR1_PATT_P_CLEAR 0 (SAR2_PATT_P_CLEAR)SAR2_PATT_P_CLEAR 0 (DATA_SAR_SEL)DATA_SAR_SEL 0 (DATA_TO_I2S)DATA_TO_I2S 0XPD_SAR1_FORCE 0XPD_SAR2_FORCE 0WAIT_ARB_CYCLE

Description

Register

Fields

START_FORCE

need_des
START

need_des
WORK_MODE

0: single mode, 1: double mode, 2: alternate mode
SAR_SEL

0: SAR1, 1: SAR2, only work for single SAR mode
SAR_CLK_GATED

need_des
SAR_CLK_DIV

SAR clock divider
SAR1_PATT_LEN

0 ~ 15 means length 1 ~ 16
SAR2_PATT_LEN

0 ~ 15 means length 1 ~ 16
SAR1_PATT_P_CLEAR

clear the pointer of pattern table for DIG ADC1 CTRL
SAR2_PATT_P_CLEAR

clear the pointer of pattern table for DIG ADC2 CTRL
DATA_SAR_SEL

1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.
DATA_TO_I2S

1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
XPD_SAR1_FORCE

force option to xpd sar1 blocks
XPD_SAR2_FORCE

force option to xpd sar2 blocks
WAIT_ARB_CYCLE

wait arbit signal stable after sar_done

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data